Generating Analog IC Layouts with LAYGEN II (SpringerBriefs by Ricardo M. F. Martins

By Ricardo M. F. Martins

This publication offers an cutting edge method for the automated iteration of analog built-in circuits (ICs) format, in accordance with template descriptions and on evolutionary computational options. A layout automation device, LAYGEN II was once applied to validate the proposed process giving precise emphasis to reusability of specialist layout wisdom and to potency on retargeting operations.     

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Additional resources for Generating Analog IC Layouts with LAYGEN II (SpringerBriefs in Applied Sciences and Technology)

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M. F. 1007/978-3-642-33146-6_3, Ó The Author(s) 2013 29 30 3 Automatic Layout Generation Fig. 1 Analog IC design flow: Closed loop device-level provide the designer with a technological and specification independent way of defining some of the most commonly used cells. The generation starts from the coarse layout definition described in the template, and finishes at the optimized target layout. In addition, since technological details are treated automatically by LAYGEN II, the designer’s efforts are focused on difficult layout issues and not on the technological dimensions details.

Comput. Aided Des. Integr. Circuits Syst. 15(8), 923–942 (1996) 30. P. Khademsameni, M. Syrzycki, A tool for automated analog CMOS layout module generation and placement, in Proceedings IEEE Canadian Conference on Electrical and Computer Engineering, vol. 1, pp. 416–421, May 2002 31. R. Castro-Lopez, O. Guerra, E. Roca, F. Fernandez, An integrated layout-synthesis approach for analog ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), 1179–1189 (2008) 32. P. Vancorenland, G. V. der Plas, M.

They treat problems related to the substitution of the devices by different ones and consequently handling the alterations in the nets. Pre-processing intends to 46 4 Placer Fig. 3 Instantiation of devices from the template example. 2 lm, L = 350 nm). 6 lm, L = 270 nm). 4 lm, L = 120 nm) automatically implement common techniques employed by the designers to increase the quality of the generated placement. These techniques are applied only for modules generated from the parametric module generator of the technology design kit, and are not applicable to imported GDSII layouts or sub-templates.

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