CMOS PLL Synthesizers: Analysis and Design by Shu K., Sánchez-Sinencio E.

By Shu K., Sánchez-Sinencio E.

This publication provides either basics and the cutting-edge of PLL synthesizer layout and research thoughts. a whole assessment of either system-level and circuit-level layout and research are coated. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is carried out in 0.35m m CMOS. It includes a high-speed and strong phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which take on pace and integration bottlenecks of PLL synthesizer elegantly.This e-book is conceived as a PLL synthesizer handbook for either academia researchers and layout engineers.

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Extra resources for CMOS PLL Synthesizers: Analysis and Design

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3 Locking time Considering that the PLL is initially locked and the frequency divide ratio changes due to channel switching, we calculate the locking time for a given frequency error. Locking time is also referred to as settling time or switching time. For the third-order loop filter shown in Fig. 3-7 (a), its transimpedance is given by: 3. 42) leads to the following PLL closed-loop phase or frequency transfer function: For simplicity, we ignore these high order terms, which are smaller than lower order terms.

169-170, Jan. 1998 A. Yamagishi, M. Ishikawa, T. Tsuneo, and S. Date, “A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication,” IEEE J. Solid-State Circuits, vol. 33, pp. 210-217, Feb. 1998 A. Madisetti, A. Kwentus, and A. Willson, “A 100-MHz, 16-b, direct digital frequency synthesizer with 100-dBc spurious-free dynamic range,” IEEE J. Solid-State Circuits, vol. 34, pp. 1034-1043, Aug. 1999 S. Mortezapour and E. Lee, “Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter,” IEEE J.

3-7 (a)), the transimpedance is Usually, and Therefore, the two non-zero poles are as follows. The bandwidth of a fourth-order charge-pump PLL is: 3. 35) is simplified as: More discussions on high-order loop filter design can be found in the literature [5]-[9]. For example, the exact relationship among and in the fourth-order PLL for maximum is derived in [9]. Note that the above phase-margin calculation is based on the continuoustime linear model of the charge-pump PLL. This model is good for loop bandwidth less than 1/10 of the reference frequency Otherwise the settling behavior will differ from the calculations significantly.

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